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Target Configuration Space
Table 7-13 · Hot-Swap Capability Register 40 Hex
Bit(s)
21:20
22
23
31:24
Bit(s)
7:0
15:8
23:16
25:24
28:26
29
30
31
Bit(s)
9:0
10
13:11
14
Type
RO
RW
RW
RO
Type
RO
RO
RO
RO
RO
RO
RO
RO
Type
RO
W
RO
RW
Description
Programming interface (PI)
Fixed at '00', programming interface 0 supports INS, EXT, LOO, and EIM.
ENUM# Status – Extraction (EXT)
When set to 1, indicates that the board is about to be extracted. Writing a '1' clears this bit.
ENUM# Status – Insertion (INS)
When set to 1, indicates that the board has just been inserted. Writing a '1' clears this bit.
Reserved. Set to 0.
Table 7-14 · Actel Capabilities Register 44, 48, or 4C Hex
Description
Actel vendor capability. Set to 09 hex.
Next Capability Pointer. Set to 40 hex.
Capability Size. Set to 8, 12, 20, or 24, depending on core configuration.
DMA_REG_LOG
Indicates the DMA register location.
0: DMA registers are not implemented.
1: DMA registers are only mapped in the PCI configuration space.
2: DMA registers are mapped to memory locations 50–5F hex of the BAR, indicated by bits 28:26.
3: DMA registers are mapped to I/O locations 50–5F hex of the BAR, indicated by bits 28:26. These two bits are set
by the DMA_REG_LOC parameter.
Indicates which BAR is used to access the DMA registers if mapped to memory or I/O space. These three bits are set
by the DMA_REG_BAR parameter.
Indicates that the backend interface is enabled and has access to the DMA registers. This bit is set by the BACKEND
parameter.
When set, indicates that the BAR overflow logic in the core is disabled. Burst accesses will simply wrap within the
BAR. This bit is set by the DISABLE_BAROV parameter.
When set, indicates that the watchdog timer in the core is disabled. The core may insert more than the allowed
number of wait cycles during a transfer. This bit is set by the DISABLE_WDOG parameter.
Table 7-15 · Interrupt Control Register 48 Hex (MASTER = 0)
Description
Reserved. Set to 0.
Flush Internal FIFOs
Only has an effect when the FIFO recovery logic is enabled. When written with a '1', all the internal FIFOs will be
flushed. When the FIFOs are flushed, any data that was stored in them will be lost. Always returns 0 when read.
Reserved. Set to 0.
External Interrupt Status
A '1' in this bit indicates an active external interrupt condition (assertion of EXT_INTn). It is cleared by writing a '1'
to this bit. It is set to 0 after reset.
v4.0
111
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